640 X 400 LCD DISPLAY W/ EL BACKLIGHT

I'm still searching for information, but this display is set up basically as TWO seperate LCD displays, one on top, and one on bottom. This isn't that common really.

(all the information I have seen points to this)

I'll be back with more on it I hope.

Well I may not have a means of using the actual LCD at this point, but I did get that giant 10" EL strip working, so that's definitely a good value, considering the other EL strips sold here are much smaller for around the same price as this whole unit. The display itself feels very solid and high quality, likely thanks to the "military application" it was designed for.

The document linked to with this LCD display is hardly legible. I found a similar device on Digi-Key which seems to use the same method of timing to display stuff on the screen. The document on digi-key is much better in quality and will help you to see how the signals work better. Here is the link:

http://media.digikey.com/pdf/Data%20Sheets/Optrex%20PDFs/DMF-50262NF-FW%20Spec.pdf

I have not actually gotten this screen yet. I ordered two and hope to play with them soon.

There is some misleading information being given
The LCD104 requires 160x242x70 pulses of xscl
this equates to 370 ns for each pulse.
The fastest PIC 18 runs at 40 mhz and requires 4 clocks per instruction
This equates to 10 mips or an instruction every 100 ns
Therefore there are just 3 instructions that can be performed by the pic per XSCL
pulse. A minimal PIC program must be load a register with the pixel bits after a memory fetch
4 lower and 4 upper and there must be a goto ( to repeat the process) which takes two intruction time slots.
So all 3 are used up before anything useful can be done. Now dropping the refresh rate might get something useful out of a PIC but the flicker will be horrible.
The pic approach is basically a non starter.
Solution:
A CPLD clocked at 20 mhz and coupled to a SRAM can perform a complex logic operation every 50 ns.
This allows 3 fetchs from memory (EX graphic text cursor layers) provided the memory
is 50 ns or less and 4 logic operations for timing control.
This 4 can be extended to 7 if a memory prefetch is overlayed with a current LCD posting. One of the 7 CPLD operations has to be reserved for DMA to the SRAM. Unlike the PIC this solution is realistic.

The previous post is to the LCD-103 which is the product above this. I thought I was going to go crazy trying to figure out where these numbers came from. So if anyone was wondering, he posted on the wrong catagory. I think. If i am mistaken, please e-mail me. I am trying still at this lcd.

electracraigy@yahoo.com